This invention relates to interconnections within a computer, in particular, to a method and apparatus capable of minimizing reflections, ringing, and delay on long CMOS interconnections in an integrated circuit, between integrated circuits, and between integrated circuits and other circuits.
Recent efforts in interconnections have revolved around minimizing the resistivity of the metals, in particular copper metallurgy for CMOS integrated circuits, used in interconnections. The problem is that minimizing the resistivity on long interconnection lines is not always the optimum solution when signal quality is also an important factor. The use of long interconnection lines where the resistivity is minimized may lead to problems with ringing and reflections on the line.
A typical long interconnection line, long being defined as an interconnection line of about 1 cm long or longer, would be a clock distribution line which is used to send clock signals to destination points within an integrated circuit or printed circuit board. Clock signal delay or skew, caused by the characteristics of the distribution line, is an important factor in the transmission of clock signals and for this reason many interconnection or distribution lines attempt to minimize resistivity. However, if signal quality at the destination point is important then consideration must also be given to minimize the reflections and ringing along the line.
FIG. 1 illustrates an interconnection which incorporates a signal source 5 which has an output impedance Zs, a long interconnection line 6, and a destination point D1. The long interconnection line 6 has an overall impedance Zo shown as line resistance RL, inductance LL, and capacitance CL. The long interconnection line 6 begins at node N2 and terminates at node N3. Connected to node N3 is a termination line with a small capacitance CS and destination point D1.
Typically, only an interconnection line 6 with minimal resistivity would be used to reduce or minimize signal delay or skew. However, an interconnection line where the resistivity is minimized would lead to potential ringing and reflection problems, which ultimately detract from the quality of the signal received. The signal quality is typically not addressed by conventional interconnection line circuits.
The problems outlined above are in large part solved by the invention which reduces reflections and ringing on CMOS interconnections by altering the geometry of the interconnection lines to obtain interconnection line characteristics which minimize reflections, ringing and delay.
Minimizing the resistivity on long interconnection lines may lead to problems with ringing and reflections on the line. As will be discussed in further detail below, the optimum choice for a long interconnection line is a line where the reflection signals at the source end N2 are attenuated by a round trip transit over the length of the line. Although for signal delay purposes the minimization of line resistivity is favorable, making the line resistance larger can improve signal quality. Therefore interconnection line characteristics and the associated geometry of the interconnection lines are considered to obtain interconnection line characteristics which will insure proper signal attenuation and signal quality.
The foregoing and other features and advantages of the invention will be more clearly understood from the following detailed description of the invention which is provided in conjunction with the accompanying drawings.